Multilayer ceramic electronic component

ABSTRACT

A multilayer ceramic electronic component includes a stacked body, and an external electrode including an underlying electrode layer containing a conductive metal and a glass component, a resin layer containing a thermosetting resin and no metal component, and a plating layer. The underlying electrode layer extends from a first or second end surface, and covers a portion of each of first and second main surfaces and first and second lateral surfaces. The resin layer covers the underlying electrode layer on the second main surface adjacent to the first or second end surface. The plating layer covers a portion of the surface of the underlying electrode layer that is not covered with the resin layer, and covers the surface of the resin layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese PatentApplication No. 2019-150801 filed on Aug. 21, 2019. The entire contentsof this application are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present disclosure relates to a multilayer ceramic electroniccomponent, such as a multilayer ceramic capacitor.

2. Description of the Related Art

In recent years, multilayer ceramic capacitors have been used in harsherenvironments than ever. For example, multilayer ceramic capacitors foruse in mobile devices, such as mobile telephones and portable musicplayers, need to withstand drop impact. Specifically, it is necessarythat multilayer ceramic capacitors do not fall out of or detach from amounting board and do not crack when subjected to drop impact.

As to multilayer ceramic capacitors for use in on-vehicle devices, suchas ECUs, they need to withstand shocks from thermal cycling.Specifically, it is necessary that multilayer ceramic capacitors do notcrack when subjected to bending stresses due to the thermal expansionand contraction of a mounting board caused by thermal cycling.

In view of the above, using a thermosetting conductive resin paste forthe external electrodes of multilayer ceramic capacitors has beenproposed. For example, Japanese Patent Laid-Open No. 11-162771 describesa countermeasure against cracking (improvement in resistance to bending)of the capacitor body, even in a harsh environment, by interposing anepoxy thermosetting conductive resin layer that contains metallic powderbetween a conventional underlying electrode layer and Ni plating layer.

With this structure, when stresses are generated, such as stresses dueto the drop impact or bending stresses due to the thermal expansion andcontraction of a mounting board caused by thermal cycling, the epoxythermosetting conductive resin layer is peeled off the underlyingelectrode layer, the peeling starting from the end of the epoxythermosetting conductive resin layer. This allows the stresses appliedto the mounting board (the deformation of the mounting board) to beabsorbed, thus preventing the capacitor body from cracking.

However, in the multilayer ceramic capacitor as described in JapanesePatent Laid-Open No. 11-162771, the epoxy thermosetting conductive resinlayer interposed between the underlying electrode layer and the Niplating layer increases the resistance between the underlying electrodelayer and the Ni plating layer, resulting in an increased equivalentseries resistance (ESR).

SUMMARY OF THE INVENTION

Preferred embodiments of the present invention provide multilayerceramic electronic components that each have a reduced ESR while havinga high resistance to cracking.

A multilayer ceramic electronic component according to a preferredembodiment of the present invention includes a stacked body, a firstexternal electrode, and a second external electrode. The stacked bodyincludes a plurality of ceramic layers and a plurality of internalelectrode layers which are stacked. The stacked body includes a firstmain surface and a second main surface opposite to each other in thestacking direction, a first end surface and a second end surfaceopposite to each other in the length direction orthogonal to orsubstantially orthogonal to the stacking direction, and a first lateralsurface and a second lateral surface opposite to each other in the widthdirection orthogonal to or substantially orthogonal to the stackingdirection and the length direction. The first external electrode isdisposed on the first end surface. The second external electrode isdisposed on the second end surface. The second main surface of thestacked body defines and functions as a mounting surface. The firstexternal electrode includes a first underlying electrode layercontaining a conductive metal, a first resin layer containing a resinand no metal component, and a first plating layer. The second externalelectrode includes a second underlying electrode layer containing aconductive metal, a second resin layer containing a resin and no metalcomponent, and a second plating layer. The first underlying electrodelayer covers the first end surface, extends from the first end surface,and covers a portion of each of the first main surface, the second mainsurface, the first lateral surface, and the second lateral surface. Thesecond underlying electrode layer covers the second end surface, extendsfrom the second end surface, and covers a portion of each of the firstmain surface, the second main surface, the first lateral surface, andthe second lateral surface. The first resin layer covers the firstunderlying electrode layer at least on the second main surface adjacentto the first end surface. The second resin layer covers the secondunderlying electrode layer at least on the second main surface adjacentto the second end surface. The first plating layer covers a portion ofthe surface of the first underlying electrode layer that is not coveredwith the first resin layer, and covers the surface of the first resinlayer. The second plating layer covers a portion of the surface of thesecond underlying electrode layer that is not covered with the secondresin layer, and covers the surface of the second resin layer.

In a multilayer ceramic electronic component according to a preferredembodiment of the present invention, the first external electrodeincludes a first resin layer containing a resin and no metal component,and the second external electrode includes a second resin layercontaining a resin and no metal component. Therefore, the multilayerceramic capacitor is able to reduce the ESR as compared to a multilayerceramic capacitor including, for example, an epoxy thermosetting resinlayer containing a metal component. This is because the multilayerceramic capacitor contains no metal component and thus forms nocurrent-carrying path, thus reducing the ESR; whereas, in a conventionalmultilayer ceramic capacitor which contains a metal component, thephysical contact of the metal component forms a current-carrying path,thus increasing the resistance and therefore increasing the ESR.

Further, even when the multilayer ceramic electronic component issubjected to stresses due to the drop impact or bending stresses due tothe thermal expansion and contraction of a mounting board caused bythermal cycling, the resin layer as described above can release thestresses applied to the mounting board (the deformation of the mountingboard), thus reducing or preventing cracking of the multilayer ceramicelectronic component.

Preferred embodiments of the present invention each provide a multilayerceramic electronic component having a reduced ESR while having a highresistance to cracking.

The above and other elements, features, steps, characteristics andadvantages of the present invention will become more apparent from thefollowing detailed description of the preferred embodiments withreference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an outside perspective view of a multilayer ceramic capacitoraccording to a first preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view of a multilayer ceramic capacitoraccording to the first preferred embodiment of the present invention,taken along line II-II of FIG. 1.

FIG. 3 is a cross-sectional view of a multilayer ceramic capacitoraccording to the first preferred embodiment of the present invention,taken along line III-III of FIG. 1.

FIG. 4 is a schematic cross-sectional view of FIG. 2.

FIG. 5 is an outside perspective view showing a multilayer ceramiccapacitor before the formation of a plating layer of externalelectrodes.

FIG. 6 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a second preferred embodiment of the presentinvention.

FIG. 7 is an outside perspective view showing the multilayer ceramiccapacitor of FIG. 6 in a state before the formation of a plating layerof external electrodes.

FIG. 8 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a third preferred embodiment of the presentinvention.

FIG. 9 is an outside perspective view showing the multilayer ceramiccapacitor of FIG. 8 in a state before the formation of a plating layerof external electrodes.

FIG. 10 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a fourth preferred embodiment of the presentinvention.

FIG. 11 is an outside perspective view showing the multilayer ceramiccapacitor of FIG. 10 in a state before the formation of a plating layerof external electrodes.

FIG. 12 is an outside perspective view showing a multilayer ceramiccapacitor according to a fifth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

FIG. 13 is an outside perspective view showing a multilayer ceramiccapacitor according to a sixth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

FIG. 14 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a seventh preferred embodiment of the presentinvention.

FIG. 15 is an outside perspective view showing the multilayer ceramiccapacitor of FIG. 14 in a state before the formation of a plating layerof external electrodes.

FIG. 16 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to an eighth preferred embodiment of the presentinvention.

FIG. 17 is an outside perspective view showing the multilayer ceramiccapacitor of FIG. 16 in a state before the formation of a plating layerof external electrodes.

FIG. 18 is an outside perspective view showing a multilayer ceramiccapacitor according to a ninth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

FIG. 19 is an outside perspective view showing a multilayer ceramiccapacitor according to a tenth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

FIG. 20A is a schematic cross-sectional view showing a structure inwhich the facing electrode portions of the internal electrode layers ofa multilayer ceramic capacitor are divided into two portions.

FIG. 20B is a schematic cross-sectional view showing a structure inwhich the facing electrode portions of the internal electrode layers ofa multilayer ceramic capacitor are divided into three portions.

FIG. 20C is a schematic cross-sectional view showing a structure inwhich the facing electrode portions of the internal electrode layers ofa multilayer ceramic capacitor are divided into four portions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described indetail with reference to the accompanying drawings.

1. First Preferred Embodiment

A multilayer ceramic capacitor will now be described as an example of amultilayer ceramic electronic component according to a first preferredembodiment of the present invention. This preferred embodiment describesa typical two-terminal capacitor as an example. However, the presentpreferred embodiment is not limited to a two-terminal capacitor, and mayalso be applied to a multi-terminal capacitor.

(1) Multilayer Ceramic Capacitor

FIG. 1 is an outside perspective view showing a multilayer ceramiccapacitor according to a first preferred embodiment of the presentinvention. FIG. 2 is a cross-sectional view taken along line II-II ofFIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III ofFIG. 1. FIG. 4 is a schematic cross-sectional view of FIG. 2. FIG. 5 isan outside perspective view showing a multilayer ceramic capacitorbefore the formation of a plating layer of external electrodes.

A multilayer ceramic capacitor 10A includes a rectangular orsubstantially rectangular parallelepiped stacked body 12 and twoexternal electrodes 24.

(A) Stacked Body

Stacked body 12 includes a plurality of ceramic layers and a pluralityof internal electrode layers 16 which are stacked. Further, stacked body12 includes a first main surface 12 a and a second main surface 12 bopposite to each other in stacking direction x, a first lateral surface12 c and a second lateral surface 12 d opposite to each other in widthdirection y orthogonal to or substantially orthogonal to stackingdirection x, and a first end surface 12 e and a second end surface 12 fopposite to each other in length direction z orthogonal to orsubstantially orthogonal to stacking direction x and width direction y.Stacked body 12 may have any suitable dimensions. Note that thedimension of stacked body 12 in length direction z is not necessarilygreater than the dimension in width direction y.

The corners and ridge lines of stacked body 12 are preferably rounded.Each corner refers to an intersection of adjacent three planes ofstacked body 12, and each ridge line refers to an intersection ofadjacent two planes of stacked body 12. First and second main surfaces12 a, 12 b, first and second lateral surfaces 12 c, 12 d, and first andsecond end surfaces 12 e, 12 f may have asperity, in part or in whole.

(i) Ceramic Layer

As shown in FIGS. 2 and 3, stacked body 12 includes an effective layerportion 15 a, a first outer layer portion 15 b 1, and a second outerlayer portion 15 b 2. Effective layer portion 15 a is a portion in whicha plurality of internal electrode layers 16 face each other in stackingdirection x, i.e., in the direction of a line connecting first andsecond main surfaces 12 a, 12 b. First outer layer portion 15 b 1includes a plurality of ceramic layers 14 located between first mainsurface 12 a and internal electrode layer 16 that is closest to firstmain surface 12 a. Second outer layer portion 15 b 2 includes aplurality of ceramic layers 14 located between second main surface 12 band internal electrode layer 16 that is closest to second main surface12 b.

First outer layer portion 15 b 1, which is located adjacent to firstmain surface 12 a of stacked body 12, includes a plurality of ceramiclayers 14 located between first main surface 12 a and internal electrodelayer 16 that is closest to first main surface 12 a.

Second outer layer portion 15 b 2, which is located adjacent to secondmain surface 12 b of stacked body 12, includes a plurality of ceramiclayers 14 located between second main surface 12 b and internalelectrode layer 16 that is closest to second main surface 12 b.

Effective layer portion 15 a is the region sandwiched between firstouter layer portion 15 b 1 and second outer layer portion 15 b 2.

The dimensions of stacked body 12 are preferably, but are not limitedto, not less than about 0.2 mm and not more than about 10.0 mm in lengthdirection z, not less than about 0.1 mm and not more than about 10.0 mmin width direction y, and not less than about 0.1 mm and not more thanabout 5.0 mm in height direction x, for example.

The number of stacked ceramic layers 14 is preferably, but is notlimited to, not less than about 15 and not more than about 200, forexample.

Ceramic layers 14 may be made of, for example, a dielectric material.The dielectric material may be, for example, a dielectric ceramiccontaining BaTiO₃, CaTiO₃, SrTiO₃, or CaZrO₃ as a primary component.With any of these dielectric materials contained as a primary component,secondary components, less in content than the primary component, may beadded in accordance with the desired characteristics of stacked body 12.Examples of the secondary components include Mn compounds, Fe compounds,Cr compounds, Co compounds, and Ni compounds.

If piezoelectric ceramic material is used for ceramic layers 14, themultilayer ceramic electronic component defines and functions as apiezoelectric component. Specific examples of the piezoelectric ceramicmaterial include lead zirconate titanate (PZT) ceramic material.

If semiconductor ceramic material is used for ceramic layers 14, themultilayer ceramic electronic component defines and functions as athermistor. Specific examples of the semiconductor ceramic materialinclude spinel ceramic material.

If magnetic ceramic material is used for ceramic layers 14, themultilayer ceramic electronic component defines and functions as aninductor. If the multilayer ceramic electronic component defines andfunctions as an inductor, internal electrode layers 16 define a coiledconductor. Specific examples of the magnetic ceramic material includeferrite ceramic material.

Each ceramic layer 14, after being fired, preferably has a thickness ofnot less than about 0.5 μm and not more than about 10 μm, for example.

(ii) Internal Electrode Layers

Stacked body 12 includes a plurality of first internal electrode layers16 a and a plurality of second internal electrode layers 16 b, whichare, for example, rectangular or substantially rectangular, as aplurality of internal electrode layers 16. The corners of the rectanglemay be rounded or may be tapered or inclined. The plurality of firstinternal electrode layers 16 a and the plurality of second internalelectrode layers 16 b are embedded such that they are alternated andequally or substantially equally spaced, with ceramic layers 14 beinginterposed therebetween, along stacking direction x of stacked body 12.

First internal electrode layers 16 a include first facing electrodeportions 18 a and first leading electrode portions 20 a. First facingelectrode portions 18 a face second internal electrode layers 16 b.First leading electrode portions 20 a are located at one end of firstinternal electrode layers 16 a and lead from facing electrode portions18 a to first end surface 12 e of stacked body 12. The end of each firstleading electrode portion 20 a is led to and exposed at first endsurface 12 e.

Second internal electrode layers 16 b include second facing electrodeportions 18 b and second leading electrode portions 20 b. Second facingelectrode portions 18 b face first internal electrode layers 16 a.Second leading electrode portions 20 b are located at one end of secondinternal electrode layers 16 b and lead from second facing electrodeportions 18 b to second end surface 12 f of stacked body 12. The end ofeach second leading electrode portion 20 b is led to and exposed atsecond end surface 12 f.

First and second facing electrode portions 18 a, 18 b may have the samewidth as, or may be larger or smaller in width than, first and secondleading electrode portions 20 a, 20 b.

As shown in FIGS. 20A to 20C, internal electrode layers 16 may includenot only first and second internal electrode layers 16 a, 16 b but alsofloating internal electrode layers 16 c that are led to neither firstend surface 12 e nor second end surface 12 f. With floating internalelectrode layers 16 c, facing electrode portions 18 may be divided intoa plurality of portions. For example, facing electrode portions 18 mayinclude two portions as shown in FIG. 20A, three portions as shown inFIG. 20B, or four portions as shown in FIG. 20C. More than four portionsare also possible. With such a structure in which facing electrodeportions 18 are divided into a plurality of portions, a plurality ofcapacitor components are provided between internal electrode layers 16a, 16 b, 16 c that face each other, with these capacitor componentsbeing connected in series. This reduces the voltage applied to eachcapacitor component, thus enabling multilayer ceramic capacitor 10A towithstand a higher voltage.

Stacked body 12 includes lateral portions (“W gaps”) 22 a between firstlateral surface 12 c and one end of first and second facing electrodeportions 18 a, 18 b in width direction y, and between second lateralsurface 12 d and the other end of first and second facing electrodeportions 18 a, 18 b in width direction y. Further, stacked body 12includes end portions (“L gaps”) 22 b between second end surface 12 fand the end of first internal electrode layers 16 a opposite to firstleading electrode portions 20 a, and between first end surface 12 e andthe end of second internal electrode layers 16 b opposite to secondleading electrode portions 20 b.

Internal electrode layers 16 may be made of an appropriate conductivematerial, such as a metal (e.g., Ni, Cu, Ag, Pd, or Au) or an alloycontaining at least one of these metals (e.g., Ag—Pd alloy). Internalelectrode layers 16 may further contain dielectric particles having thesame or substantially the same composition as the ceramic contained inceramic layers 14.

Each internal electrode layer 16 preferably has a thickness of not lessthan about 0.2 μm and not more than about 2.0 μm, for example. Thenumber of internal electrode layers 16 is preferably not less than about15 and not more than about 200, for example.

(B) External Electrodes

External electrodes 24 are disposed on first and second end surfaces 12e, 12 f of stacked body 12. External electrodes 24 include a firstexternal electrode 24 a and a second external electrode 24 b. Each offirst and second external electrodes 24 a, 24 b includes an underlyingelectrode layer 26 connected to internal electrode layers 16, a resinlayer 28 provided on underlying electrode layer 26, and a plating layer30 provided on resin layer 28.

First external electrode 24 a covers first end surface 12 e of stackedbody 12, extends from first end surface 12 e, and covers a portion ofeach of first main surface 12 a, second main surface 12 b, first lateralsurface 12 c, and second lateral surface 12 d. In this case, firstexternal electrode 24 a is electrically connected to first leadingelectrode portions 20 a of first internal electrode layers 16 a.

Second external electrode 24 b covers second end surface 12 f of stackedbody 12, extends from second end surface 12 f, and covers a portion ofeach of first main surface 12 a, second main surface 12 b, first lateralsurface 12 c, and second lateral surface 12 d. In this case, secondexternal electrode 24 b is electrically connected to second leadingelectrode portions 20 b of second internal electrode layer 16 b.

In stacked body 12, first facing electrode portions 18 a of firstinternal electrode layers 16 a and second facing electrode portions 18 bof second internal electrode layers 16 b face each other, with ceramiclayers 14 being interposed therebetween, thus generating capacitance.This provides a capacitance between first external electrode 24 a, towhich first internal electrode layers 16 a are connected, and secondexternal electrode 24 b, to which second internal electrode layers 16 bare connected. The characteristics of capacitor is thus provided.

First external electrode 24 a includes a first underlying electrodelayer 26 a, a first resin layer 28 a, and a first plating layer 30 a.First underlying electrode layer 26 a contains a conductive metal and aglass component. First resin layer 28 a contains a thermosetting resinand no metal component.

Second external electrode 24 b includes a second underlying electrodelayer 26 b, a second resin layer 28 b, and a second plating layer 30 b.Second underlying electrode layer 26 b contains a conductive metal and aglass component. Second resin layer 28 b contains a thermosetting resinand no metal component.

(i) Underlying Electrode Layer

Underlying electrode layer 26 includes first and second underlyingelectrode layers 26 a, 26 b.

First underlying electrode layer 26 a covers first end surface 12 e ofstacked body 12, extends from first end surface 12 e, and covers aportion of each of first main surface 12 a, second main surface 12 b,first lateral surface 12 c, and second lateral surface 12 d.

Second underlying electrode layer 26 b covers second end surface 12 f ofstacked body 12, extends from second end surface 12 f, and covers aportion of each of first main surface 12 a, second main surface 12 b,first lateral surface 12 c, and second lateral surface 12 d.

Underlying electrode layer 26 contains a conductive metal and a glasscomponent. The metal in underlying electrode layer 26 preferablyincludes at least one selected from Cu, Ni, Ag, Pb, Pd, Ag—Pb alloy,Ag—Pd alloy, and Au, for example. The glass in underlying electrodelayer 26 preferably includes at least one selected from B, Si, Ba, Mg,Al, and Li, for example.

Underlying electrode layer 26 may include a plurality of layers.Underlying electrode layer 26 is produced by applying a conductive pastecontaining glass and metal to stacked body 12 and then baking it. Thebaking may be performed simultaneously with or after the firing ofceramic layers 14 and internal electrode layers 16.

Underlying electrode layer 26 preferably has a thickness of, forexample, not less than about 10 μm and not more than about 150 μm oneach of first and second end surfaces 12 e, 12 f, at its center. Withsuch a thickness, solder will come into contact with the plating ofexternal electrode 24 at an acute angle. Thus, when a stress is appliedfrom the solder to the plating during thermal shock cycling, a largerproportion of the stress is a component parallel or substantiallyparallel to the plating plane. This can reduce the occurrence of soldercracking. Underlying electrode layer 26 preferably has a thickness of,for example, not less than about 5 μm and not more than about 50 μm oneach of first main surface 12 a, second main surface 12 b, first lateralsurface 12 c, and second lateral surface 12 d, at its center orapproximate center.

Each external electrode 24 may include only a plating layer, with nounderlying electrode layer 26. A structure including a plating layerwith no underlying electrode layer will now be described.

For each of first and second external electrodes 24 a, 24 b, a platinglayer may be directly provided on the surface of stacked body 12, withno underlying electrode layer. That is, multilayer ceramic capacitor 10Amay include a plating layer electrically connected to first internalelectrode layers 16 a or second internal electrode layers 16 b. In thiscase, a catalyst may be applied to the surface of stacked body 12 as apretreatment before the plating layer is provided.

The plating layer preferably includes a lower plating electrode providedon the surface of stacked body 12, and an upper plating electrodeprovided on the surface of the lower plating electrode.

Each of the lower and upper plating electrodes preferably contains atleast one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn; oran alloy containing any of these metals, for example.

The lower plating electrode is preferably made of, for example, Ni,which can define and function as a barrier against solder. The upperplating electrode is preferably made of, for example, Sn or Au, whichhas good solder wettability. If first and second internal electrodelayers 16 a, 16 b are made of Ni for example, the lower platingelectrode is preferably made of Cu, which has good bondability to Ni.The upper plating electrode is optional, that is, each of first andsecond external electrodes 24 a, 24 b may include only of the lowerplating electrode.

The plating layer may include the upper plating electrode as anoutermost layer, or may include an additional plating electrode on thesurface of the upper plating electrode.

With no underlying electrode layer, each plating layer preferably has athickness of not less than about 1 μm and not more than about 15 μm, forexample. The plating layer is preferably free from glass. The percentageof metal in the plating layer per unit volume is preferably about 99 vol% or more, for example.

(ii) Resin Layer

Resin layer 28 includes first resin layer 28 a and second resin layer 28b.

First resin layer 28 a covers first underlying electrode layer 26 a onsecond main surface 12 b adjacent to first end surface 12 e.

Second resin layer 28 b covers second underlying electrode layer 26 b onsecond main surface 12 b adjacent to second end surface 12 f.

Resin layer 28 contains a thermosetting resin and no metal component. Asa specific example of the thermosetting resin contained in resin layer28, any of various publicly known thermosetting resins may be used, suchas epoxy resins, phenolic resins, urethane resins, silicone resins, andpolyimide resins. Among these, epoxy resin is one of the most preferableresins due to its excellent heat resistance, moisture resistance, andadhesion. Resin layer 28 preferably contains a curing agent as well asthermosetting resin. If an epoxy resin is used as the base resin, thecuring agent may be any of various publicly known compounds, such as,for example, phenolic compounds, amine compounds, acid anhydridecompounds, and imidazole compounds.

While the resin used for resin layer 28 is preferably a thermosettingresin, other types of resin may also be used, such as a room-temperaturecurable resin, a photo-curable resin, or an electron beam curable resin,for example.

Resin layer 28, which contains a thermosetting resin, is more flexiblethan, for example, plating layer 30 and underlying electrode layer 26.Accordingly, even if multilayer ceramic capacitor 10A is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 28 can define and function as a buffer layer, thuspreventing cracking of multilayer ceramic capacitor 10A.

Resin layer 28 preferably has a thickness of, but is not limited to, notless than about 10 μm and not more than about 30 μm for example.

(iii) Plating Layer

Plating layer 30 includes first and second plating layers 30 a, 30 b.

First plating layer 30 a covers the surface of first resin layer 28 aand a portion of the surface of first underlying electrode layer 26 athat is not covered with first resin layer 28 a. Thus, first platinglayer 30 a is directly in contact with a portion of first underlyingelectrode layer 26 a that is exposed through first resin layer 28 a.Specifically, first plating layer 30 a covers first underlying electrodelayer 26 a located on first main surface 12 a, on first lateral surface12 c, on second lateral surface 12 d, and on first end surface 12 e; andcovers first resin layer 28 a located on second main surface 12 b.

Second plating layer 30 b covers the surface of second resin layer 28 band a portion of the surface of second underlying electrode layer 26 bthat is not covered with second resin layer 28 b. Thus, second platinglayer 30 b is directly in contact with a part of second underlyingelectrode layer 26 b that is exposed through second resin layer 28 b.Specifically, second plating layer 30 b covers second underlyingelectrode layer 26 b located on first main surface 12 a, on firstlateral surface 12 c, on second lateral surface 12 d, and on second endsurface 12 f; and covers second resin layer 28 b located on second mainsurface 12 b.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 28 a interposed therebetween, onfirst main surface 12 a, first lateral surface 12 c, second lateralsurface 12 d, and first end surface 12 e. In second external electrode24 b, second plating layer 30 b is directly in contact with secondunderlying electrode layer 26 b, with no high-resistivity second resinlayer 28 b interposed therebetween, on first main surface 12 a, firstlateral surface 12 c, second lateral surface 12 d, and second endsurface 12 f. Thus, first and second external electrodes 24 a, 24 benable a reduced equivalent series resistance (ESR).

The metallic material of first and second plating layers 30 a, 30 bpreferably includes at least one selected from Cu, Ni, Ag, Pd, Ag—Pdalloy, and Au, for example.

Each of first and second plating layers 30 a, 30 b may include aplurality of layers. First plating layer 30 a preferably has adouble-layer structure including a Ni plating layer and a Sn platinglayer, for example. Second plating layer 30 b also has a double-layerstructure preferably including a Ni plating layer and a Sn platinglayer, for example. The Ni plating layer can prevent resin layer 28 andunderlying electrode layer 26 from being eroded by the mounting solderwhen multilayer ceramic capacitor 10A is mounted. The Sn plating layercan improve the solder wettability when multilayer ceramic capacitor 10Ais mounted, thus enabling easy mounting of multilayer ceramic capacitor10A. Each plating layer 30 preferably has a thickness of not less thanabout 1 μm and not more than about 15 μm, for example.

Where the dimension of multilayer ceramic capacitor 10A in lengthdirection z is denoted by L dimension, L dimension is preferably notless than about 0.2 mm and not more than about 10 mm, for example. Wherethe dimension of multilayer ceramic capacitor 10A in width direction yis denoted by W dimension, W dimension is preferably not less than about0.1 mm and not more than about 10 mm, for example. Where the dimensionof multilayer ceramic capacitor 10A in stacking direction x is denotedby T dimension, T dimension is preferably not less than about 0.1 mm andnot more than about 5 mm, for example.

In multilayer ceramic capacitor 10A shown in FIG. 1, first externalelectrode 24 a includes first resin layer 28 a containing a resin and nometal component, and second external electrode 24 b includes secondresin layer 28 b containing a resin and no metal component. Therefore,multilayer ceramic capacitor 10A can reduce the ESR as compared to amultilayer ceramic capacitor including, for example, an epoxythermosetting resin layer containing a metal component. This is becausethe multilayer ceramic capacitor according to the present preferredembodiment contains no metal component and thus includes nocurrent-carrying path, thereby reducing the ESR. Whereas, in aconventional multilayer ceramic capacitor which contains a metalcomponent, the physical contact of the metal component providing acurrent-carrying path, thereby increasing the resistance and thereforeincreasing the ESR.

Further, even when the multilayer ceramic electronic component issubjected to stresses due to the drop impact or bending stresses due tothe thermal expansion and contraction of a mounting board caused bythermal cycling, resin layer 28 as described above can release thestresses applied to the mounting board (the deformation of the mountingboard), thus reducing or preventing cracking of the multilayer ceramicelectronic component.

(2) Method for Manufacturing Multilayer Ceramic Capacitor

Description will now be provided of one preferred embodiment of a methodfor manufacturing multilayer ceramic capacitor 10A in the firstpreferred embodiment having the structure as described above.

First, ceramic green sheets for producing ceramic layers 14, aninternal-electrode conductive paste for producing internal electrodelayers 16, and an external-electrode conductive paste for producingunderlying electrode layer 26 of external electrodes 24 are prepared.The ceramic green sheets, the internal-electrode conductive paste, andthe external-electrode conductive paste contain binders and solvents,which may be any of publicly known organic binders and organic solvents.

The ceramic green sheets are printed with the internal-electrodeconductive paste in a predetermined pattern, so that an internalelectrode pattern is formed on the ceramic green sheets. Any of publiclyknown methods may be used for printing the internal-electrode conductivepaste, such as screen printing or gravure printing, for example.

Then, a predetermined number of ceramic green sheets for outer layerwith no internal electrode pattern are stacked. On these sheets, ceramicgreen sheets with the internal electrode pattern printed thereon arestacked one after another. Further, a predetermined number of ceramicgreen sheets for outer layer are stacked. Thus, a mother stacked body isproduced. If necessary, the mother stacked body may be compressed instacking direction x by, for example, hydrostatic pressing.

Then, the mother stacked body is cut into pieces having a predeterminedshape and size, thus producing raw stacked body chips. At this time, theridge lines and corners of each raw stacked body chip may be rounded by,for example, barrel polishing. Then, each raw stacked body chip that hasbeen cut out is fired, thus producing stacked body 12. The temperatureof firing the raw stacked body chip is preferably not less than about900° C. and not more than about 1400° C., for example, depending on thematerials of the ceramic and internal-electrode conductive paste.

Next, first and second external electrodes 24 a, 24 b are formedrespectively on first and second end surfaces 12 e, 12 f of stacked body12. Specifically, after stacked body 12 is fired, a paste for underlyingelectrode layers containing a conductive metal and a glass component isapplied by, for example, dipping to first and second end surfaces 12 e,12 f of stacked body 12, and is then baked. Thus, first underlyingelectrode layer 26 a of first external electrode 24 a and secondunderlying electrode layer 26 b of second external electrode 24 b areformed. The baking temperature is preferably not less than about 700° C.and not more than about 900° C., for example.

Instead of underlying electrode layer 26, an underlying plating layermay be formed on first and second end surfaces 12 e, 12 f of stackedbody 12. In this case, first and second end surfaces 12 e, 12 f ofstacked body 12 are plated so that an underlying plating layer is formedon the portion where leading electrode portions 20 of internal electrodelayers 16 are exposed. Any one of electrolytic plating and electrolessplating may be used for plating. However, electrolytic plating istypically preferred, since electroless plating would require apretreatment with a catalyst to increase the rate of plating depositionand thus complicates the process. As a plating technique, for example,barrel plating is preferably used. If necessary, the underlying platinglayer has a double-layer structure including a lower plating and anupper plating.

Then, resin layer 28 is formed. Specifically, a resin-layer paste thatcontains a thermosetting resin and no metal component is applied, sothat the resin-layer paste covers first underlying electrode layer 26 alocated on second main surface 12 b adjacent to first end surface 12 e.Thus, first resin layer 28 a is formed. Similarly, a resin-layer pastethat contains a thermosetting resin and no metal component is applied,so that the resin-layer paste covers second underlying electrode layer26 b located on second main surface 12 b adjacent to second end surface12 f. Thus, second resin layer 28 b is formed.

In order to form first and second resin layers 28 a, 28 b only on secondmain surface 12 b, the following example of a method may be used. First,stacked bodies 12 are arranged on an array plate, with their second mainsurface 12 b facing upward. Then, second main surface 12 b is masked, sothat only a portion where a resin layer is to be formed is exposed.Then, a resin-layer paste is applied to second main surface 12 b byscreen printing, for example. After that, the masking is removed.

As an alternative method to form first and second resin layers 28 a, 28b only on second main surface 12 b, the following example of a methodmay also be used. First, a resin-layer paste is applied by, for example,dipping, not only to second main surface 12 b but also to othersurfaces. Then, a superfluous resin-layer paste on the surfaces otherthan second main surface 12 b is removed.

The resin-layer paste is then heat-treated at, for example, atemperature of not less than about 250° C. and not more than about 550°C. so that the thermosetting resin can be thermally cured, thus formingresin layer 28. The heat treatment is performed preferably under a N₂atmosphere, for example. In order to prevent the scattering ofthermosetting resin and the oxidation of metallic powder, the oxygenconcentration is preferably about 100 ppm or less, for example.

Next, plating layer 30 is formed so that it covers the surface of resinlayer 28 and covers a portion of the surface of underlying electrodelayer 26 that is not covered with resin layer 28. Plating layer 30 has adouble-layer structure including a Ni plating layer and a Sn platinglayer on the Ni plating layer. The Ni plating layer and the Sn platinglayer are formed in sequence by, for example, barrel plating.

Through the processes described above, multilayer ceramic capacitor 10Ais manufactured.

2. Second Preferred Embodiment

FIG. 6 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a second preferred embodiment of the presentinvention. FIG. 7 is an outside perspective view showing the multilayerceramic capacitor of FIG. 6 in a state before the formation of a platinglayer of external electrodes.

A multilayer ceramic capacitor 10B according to the second preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 128.Here, redundant description is omitted.

Resin layer 128 includes a first resin layer 128 a and a second resinlayer 128 b.

First resin layer 128 a covers a portion of first underlying electrodelayer 26 a located on second main surface 12 b adjacent to first endsurface 12 e and extending from second main surface 12 b to first endsurface 12 e.

Second resin layer 128 b covers a portion of second underlying electrodelayer 26 b located on second main surface 12 b adjacent to second endsurface 12 f and extending from second main surface 12 b to second endsurface 12 f.

Accordingly, even if multilayer ceramic capacitor 10B is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 128 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10B.

Further, first plating layer 30 a covers first underlying electrodelayer 26 a located on first main surface 12 a, on first lateral surface12 c, on second lateral surface 12 d, and on first end surface 12 e; andcovers first resin layer 128 a located on second main surface 12 b andon first end surface 12 e.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on first main surface 12 a, on first lateral surface 12 c, onsecond lateral surface 12 d, and on second end surface 12 f; and coverssecond resin layer 128 b located on second main surface 12 b and onsecond end surface 12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 128 a interposed therebetween, onfirst main surface 12 a, first lateral surface 12 c, second lateralsurface 12 d, and first end surface 12 e. In second external electrode24 b, second plating layer 30 b is directly in contact with secondunderlying electrode layer 26 b, with no high-resistivity second resinlayer 128 b interposed therebetween, on first main surface 12 a, firstlateral surface 12 c, second lateral surface 12 d, and second endsurface 12 f. Thus, first and second external electrodes 24 a, 24 benable a reduced equivalent series resistance (ESR).

In order to form first and second resin layers 128 a, 128 b only on aportion of second main surface 12 b and on a portion of adjacent firstand second end surfaces 12 e, 12 f, the following example of a methodmay be used. First, stacked bodies 12 are arranged on an array plate,with their second main surface 12 b facing upward. Then, second mainsurface 12 b is masked, so that only a portion where a resin layer is tobe formed is exposed. Then, a resin-layer paste is applied to secondmain surface 12 b by screen printing, for example. After that, themasking is removed. Similarly, a resin-layer paste is also applied tofirst and second end surfaces 12 e, 12 f by screen printing, forexample.

As an alternative method to form first and second resin layers 128 a,128 b only on a portion of second main surface 12 b and on a portion ofadjacent first and second end surfaces 12 e, 12 f, the following exampleof a method may also be used. First, a resin-layer paste is applied by,for example, dipping, not only to second main surface 12 b and adjacentfirst and second end surfaces 12 e, 12 f but also to other surfaces.Then, a superfluous resin-layer paste on the surfaces other than secondmain surface 12 b and adjacent first and second end surfaces 12 e, 12 fis removed.

3. Third Preferred Embodiment

FIG. 8 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a third preferred embodiment of the presentinvention. FIG. 9 is an outside perspective view showing the multilayerceramic capacitor of FIG. 8 in a state before the formation of a platinglayer of external electrodes.

A multilayer ceramic capacitor 10C according to the third preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 228.Here, redundant description is omitted.

Resin layer 228 includes a first resin layer 228 a and a second resinlayer 228 b.

First resin layer 228 a covers first underlying electrode layer 26 a onfirst main surface 12 a adjacent to first end surface 12 e and on secondmain surface 12 b adjacent to first end surface 12 e.

Second resin layer 228 b covers second underlying electrode layer 26 bon first main surface 12 a adjacent to second end surface 12 f and onsecond main surface 12 b adjacent to second end surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10C is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 228 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10C.

Further, both first and second main surfaces 12 a, 12 b can define andfunction as a mounting surface, which eliminates the need fordistinction depending on the direction on an automatic taping machine.

First plating layer 30 a covers first underlying electrode layer 26 alocated on first lateral surface 12 c, on second lateral surface 12 d,and on first end surface 12 e; and covers first resin layer 228 alocated on first main surface 12 a and on second main surface 12 b.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on first lateral surface 12 c, on second lateral surface 12 d,and on second end surface 12 f; and covers second resin layer 228 blocated on first main surface 12 a and on second main surface 12 b.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 228 a interposed therebetween, onfirst lateral surface 12 c, second lateral surface 12 d, and first endsurface 12 e. In second external electrode 24 b, second plating layer 30b is directly in contact with second underlying electrode layer 26 b,with no high-resistivity second resin layer 228 b interposedtherebetween, on first lateral surface 12 c, second lateral surface 12d, and second end surface 12 f. Thus, first and second externalelectrodes 24 a, 24 b enables a reduced equivalent series resistance(ESR).

In order to form first and second resin layers 228 a, 228 b only onfirst and second main surfaces 12 a, 12 b, the following example of amethod may be used. First, stacked bodies 12 are arranged on an arrayplate, with their first main surface 12 a facing upward. Then, firstmain surface 12 a is masked, so that only a portion where a resin layeris to be formed is exposed. Then, a resin-layer paste is applied tofirst main surface 12 a by screen printing, for example. After that, themasking is removed. Similarly, a resin-layer paste is also applied tosecond main surface 12 b by screen printing, for example.

As an alternative method to form first and second resin layers 228 a,228 b only on first and second main surfaces 12 a, 12 b, the followingexample of a method may also be used. First, a resin-layer paste isapplied by, for example, dipping, not only to first and second mainsurfaces 12 a, 12 b but also to other surfaces. Then, a superfluousresin-layer paste on the surfaces other than first and second mainsurfaces 12 a, 12 b is removed.

4. Fourth Preferred Embodiment

FIG. 10 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a fourth preferred embodiment of the presentinvention. FIG. 11 is an outside perspective view showing the multilayerceramic capacitor of FIG. 10 in a state before the formation of aplating layer of external electrodes.

A multilayer ceramic capacitor 10D according to the fourth preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 328.Here, redundant description is omitted.

Resin layer 328 includes a first resin layer 328 a and a second resinlayer 328 b.

First resin layer 328 a covers a portion of first underlying electrodelayer 26 a located on first main surface 12 a adjacent to first endsurface 12 e and extending from first main surface 12 a to first endsurface 12 e. First resin layer 328 a also covers a portion of firstunderlying electrode layer 26 a located on second main surface 12 badjacent to first end surface 12 e and extending from second mainsurface 12 b to first end surface 12 e. Second resin layer 328 b coversa portion of second underlying electrode layer 26 b located on firstmain surface 12 a adjacent to second end surface 12 f and extending fromfirst main surface 12 a to second end surface 12 f. Second resin layer328 b also covers a portion of second underlying electrode layer 26 blocated on second main surface 12 b adjacent to second end surface 12 fand extending from second main surface 12 b to second end surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10D is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 328 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10D.

Further, both first and second main surfaces 12 a, 12 b can define andfunction as a mounting surface, which eliminates the need fordistinction depending on the direction on an automatic taping machine.

First plating layer 30 a covers first underlying electrode layer 26 alocated on first lateral surface 12 c, on second lateral surface 12 d,and on first end surface 12 e; and covers first resin layer 328 alocated on first main surface 12 a, on second main surface 12 b, and onfirst end surface 12 e.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on first lateral surface 12 c, on second lateral surface 12 d,and on second end surface 12 f; and covers second resin layer 328 blocated on first main surface 12 a, on second main surface 12 b, and onsecond end surface 12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 328 a interposed therebetween, onfirst lateral surface 12 c, second lateral surface 12 d, and first endsurface 12 e. In second external electrode 24 b, second plating layer 30b is directly in contact with second underlying electrode layer 26 b,with no high-resistivity second resin layer 328 b interposedtherebetween, on first lateral surface 12 c, second lateral surface 12d, and second end surface 12 f. Thus, first and second externalelectrodes 24 a, 24 b enable a reduced equivalent series resistance(ESR).

In order to form first and second resin layers 328 a, 328 b only on aportion of first and second main surfaces 12 a, 12 b and on a portion ofadjacent first and second end surfaces 12 e, 12 f, the following exampleof a method may be used. First, stacked bodies 12 are arranged on anarray plate, with their second main surface 12 b facing upward. Then,second main surface 12 b is masked, so that only a portion where a resinlayer is to be formed is exposed. Then, a resin-layer paste is appliedto second main surface 12 b by screen printing, for example. After that,the masking is removed. Similarly, a resin-layer paste is also appliedto first main surface 12 a and first and second end surfaces 12 e, 12 fby screen printing, for example.

As an alternative method to form first and second resin layers 328 a,328 b, the following example of a method may also be used. First, aresin-layer paste is applied by, for example, dipping, not only to firstand second main surfaces 12 a, 12 b and adjacent first and second endsurfaces 12 e, 12 f but also to other surfaces. Then, a superfluousresin-layer paste on the surfaces other than first and second mainsurfaces 12 a, 12 b and adjacent first and second end surfaces 12 e, 12f is removed.

5. Fifth Preferred Embodiment

FIG. 12 is an outside perspective view showing a multilayer ceramiccapacitor according to a fifth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

A multilayer ceramic capacitor 10E according to the fifth preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 428.Here, redundant description is omitted.

Resin layer 428 includes a first resin layer 428 a and a second resinlayer 428 b.

First resin layer 428 a covers first underlying electrode layer 26 alocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to first end surface 12 e.

Second resin layer 428 b covers second underlying electrode layer 26 blocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to second end surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10E is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 428 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10E.

Further, all of first and second main surfaces 12 a, 12 b and first andsecond lateral surfaces 12 c, 12 d can define and function as a mountingsurface, which eliminates the need for distinction depending on thedirection on an automatic taping machine.

First plating layer 30 a covers first underlying electrode layer 26 alocated on first end surface 12 e; and covers first resin layer 428 alocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to first end surface 12 e.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on second end surface 12 f; and covers second resin layer 428 blocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to second end surface 12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 428 a interposed therebetween, onfirst end surface 12 e. In second external electrode 24 b, secondplating layer 30 b is directly in contact with second underlyingelectrode layer 26 b, with no high-resistivity second resin layer 428 binterposed therebetween, on second end surface 12 f. Thus, first andsecond external electrodes 24 a, 24 b enables a reduced equivalentseries resistance (ESR).

In order to form first and second resin layers 428 a, 428 b only on aportion of first and second main surfaces 12 a, 12 b and on a portion ofadjacent first and second lateral surfaces 12 c, 12 d, the followingexample of a method may be used. First, stacked bodies 12 are arrangedon an array plate, with their second main surface 12 b facing upward.Then, second main surface 12 b is masked, so that only a portion where aresin layer is to be formed is exposed. Then, a resin-layer paste isapplied to second main surface 12 b by screen printing, for example.After that, the masking is removed. Similarly, a resin-layer paste isalso applied to first main surface 12 a and first and second lateralsurfaces 12 c, 12 d by screen printing, for example.

As an alternative method to form first and second resin layers 428 a,428 b, the following example of a method may also be used. First, aresin-layer paste is applied by, for example, dipping, to all the sixsurfaces of stacked body 12. Then, a superfluous resin-layer paste onthe two surfaces, first and second end surfaces 12 e, 12 f, only has tobe removed. This allows easy formation of first and second resin layers428 a, 428 b.

6. Sixth Preferred Embodiment

FIG. 13 is an outside perspective view showing a multilayer ceramiccapacitor according to a sixth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

A multilayer ceramic capacitor 10F according to the sixth preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 528.Here, redundant description is omitted.

Resin layer 528 includes a first resin layer 528 a and a second resinlayer 528 b.

First resin layer 528 a covers first underlying electrode layer 26 alocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to first end surface 12 e.First resin layer 528 a further extends from these surfaces and covers aportion of first underlying electrode layer 26 a located on first endsurface 12 e.

Second resin layer 528 b covers second underlying electrode layer 26 blocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to second end surface 12 f.Second resin layer 528 b further extends from these surfaces and coversa portion of second underlying electrode layer 26 b located on secondend surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10F is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 528 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10F.

Further, all of first and second main surfaces 12 a, 12 b and first andsecond lateral surfaces 12 c, 12 d can define and function as a mountingsurface, which eliminates the need for distinction depending on thedirection on an automatic taping machine.

Further, since the thin portion of underlying electrode layer 26 (at andaround the corners and ridge lines) is covered with resin layer 528, themoisture resistance reliability can be improved.

First plating layer 30 a covers first resin layer 528 a located on firstand second main surfaces 12 a, 12 b and on first and second lateralsurfaces 12 c, 12 d adjacent to first end surface 12 e, and located onfirst end surface 12 e; and covers first underlying electrode layer 26 aexposed through first resin layer 528 a on first end surface 12 e.

Second plating layer 30 b covers second resin layer 528 b located onfirst and second main surfaces 12 a, 12 b and on first and secondlateral surfaces 12 c, 12 d adjacent to second end surface 12 f, andlocated on second end surface 12 f; and covers second underlyingelectrode layer 26 b exposed through second resin layer 528 b on secondend surface 12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 528 a interposed therebetween, onfirst end surface 12 e. In second external electrode 24 b, secondplating layer 30 b is directly in contact with second underlyingelectrode layer 26 b, with no high-resistivity second resin layer 528 binterposed therebetween, on second end surface 12 f. Thus, first andsecond external electrodes 24 a, 24 b enable a reduced equivalent seriesresistance (ESR).

In order to form first and second resin layers 528 a, 528 b only on aportion of first and second main surfaces 12 a, 12 b and on a portion ofadjacent first lateral surface 12 c, second lateral surface 12 d, firstend surface 12 e, and second end surface 12 f, the following example ofa method may be used. First, stacked bodies 12 are arranged on an arrayplate, with their second main surface 12 b facing upward. Then, secondmain surface 12 b is masked, so that only a portion where a resin layeris to be formed is exposed. Then, a resin-layer paste is applied tosecond main surface 12 b by screen printing, for example. After that,the masking is removed. Similarly, a resin-layer paste is also appliedto first main surface 12 a, first and second lateral surfaces 12 c, 12d, and first and second end surfaces 12 e, 12 f by screen printing, forexample.

As an alternative method to form first and second resin layers 528 a,528 b, the following example of a method may also be used. First, aresin-layer paste is applied by, for example, dipping, to all the sixsurfaces of stacked body 12. Then, a superfluous resin-layer paste onthe two surfaces, first and second end surfaces 12 e, 12 f, only has tobe removed. This allows easy formation of first and second resin layers528 a, 528 b.

7. Seventh Preferred Embodiment

FIG. 14 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to a seventh preferred embodiment of the presentinvention. FIG. 15 is an outside perspective view showing the multilayerceramic capacitor of FIG. 14 in a state before the formation of aplating layer of external electrodes.

A multilayer ceramic capacitor 10G according to the seventh preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 628.Here, redundant description is omitted.

Resin layer 628 includes a first resin layer 628 a and a second resinlayer 628 b.

First resin layer 628 a covers first underlying electrode layer 26 alocated on second main surface 12 b adjacent to first end surface 12 e,and covers a portion of first underlying electrode layer 26 a located ata central portion of first end surface 12 e.

Second resin layer 628 b covers second underlying electrode layer 26 blocated on second main surface 12 b adjacent to second end surface 12 f,and covers a portion of second underlying electrode layer 26 b locatedat a central portion of second end surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10G is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 628 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10G.

Resin layer 628 also defines and functions as a protective layer toprevent water from entering internal electrode layers 16 throughunderlying electrode layer 26, thus improving the resistance tomoisture.

First plating layer 30 a covers first underlying electrode layer 26 alocated on first main surface 12 a, on first and second lateral surfaces12 c, 12 d, and on first end surface 12 e; and covers first resin layer628 a located on second main surface 12 b and on first end surface 12 e.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on first main surface 12 a, on first and second lateral surfaces12 c, 12 d, and on second end surface 12 f; and covers second resinlayer 628 b located on second main surface 12 b and on second endsurface 12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 628 a interposed therebetween, onfirst main surface 12 a, first lateral surface 12 c, second lateralsurface 12 d, and first end surface 12 e. In second external electrode24 b, second plating layer 30 b is directly in contact with secondunderlying electrode layer 26 b, with no high-resistivity second resinlayer 628 b interposed therebetween, on first main surface 12 a, firstlateral surface 12 c, second lateral surface 12 d, and second endsurface 12 f. Thus, first and second external electrodes 24 a, 24 benable a reduced equivalent series resistance (ESR).

In order to form first and second resin layers 628 a, 628 b only on aportion of second main surface 12 b and on a portion of adjacent firstand second end surfaces 12 e, 12 f, the following example of a methodmay be used. First, stacked bodies 12 are arranged on an array plate,with their second main surface 12 b facing upward. Then, second mainsurface 12 b is masked, so that only a portion where a resin layer is tobe formed is exposed. Then, a resin-layer paste is applied to secondmain surface 12 b by screen printing, for example. After that, themasking is removed. Similarly, a resin-layer paste is also applied tofirst and second end surfaces 12 e, 12 f by screen printing, forexample.

As an alternative method to form first and second resin layers 628 a,628 b (only on a portion of second main surface 12 b and on a portion ofadjacent first and second end surfaces 12 e, 12 f), the followingexample of a method may also be used. First, a resin-layer paste isapplied by, for example, dipping, not only to second main surface 12 band adjacent first and second end surfaces 12 e, 12 f but also to othersurfaces. Then, a superfluous resin-layer paste on the surfaces otherthan second main surface 12 b and adjacent first and second end surfaces12 e, 12 f is removed. This allows easy formation of first and secondresin layers 628 a, 628 b.

8. Eighth Preferred Embodiment

FIG. 16 is a schematic cross-sectional view showing a multilayer ceramiccapacitor according to an eighth preferred embodiment of the presentinvention. FIG. 17 is an outside perspective view showing the multilayerceramic capacitor of FIG. 16 in a state before the formation of aplating layer of external electrodes.

A multilayer ceramic capacitor 10H according to the eighth preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 728.Here, redundant description is omitted.

Resin layer 728 includes a first resin layer 728 a and a second resinlayer 728 b.

First resin layer 728 a covers first underlying electrode layer 26 alocated on first and second main surfaces 12 a, 12 b adjacent to firstend surface 12 e; and covers a portion of first underlying electrodelayer 26 a located at the central portion of first end surface 12 e.

Second resin layer 728 b covers second underlying electrode layer 26 blocated on first and second main surfaces 12 a, 12 b adjacent to secondend surface 12 f; and covers a portion of second underlying electrodelayer 26 b located at the central portion of second end surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10H is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 728 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10H.

Resin layer 728 also defines and functions as a protective layer toprevent water from entering internal electrode layers 16 throughunderlying electrode layer 26, thus improving the resistance tomoisture.

Further, both of first and second main surfaces 12 a, 12 b can defineand function as a mounting surface, which eliminates the need fordistinction depending on the direction on an automatic taping machine.

First plating layer 30 a covers first underlying electrode layer 26 alocated on first lateral surface 12 c, on second lateral surface 12 d,and on first end surface 12 e; and covers first resin layer 728 alocated on first main surface 12 a, on second main surface 12 b, and onfirst end surface 12 e.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on first lateral surface 12 c, on second lateral surface 12 d,and on second end surface 12 f; and covers second resin layer 728 blocated on first main surface 12 a, on second main surface 12 b, and onsecond end surface 12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 728 a interposed therebetween, onfirst lateral surface 12 c, second lateral surface 12 d, and first endsurface 12 e. In second external electrode 24 b, second plating layer 30b is directly in contact with second underlying electrode layer 26 b,with no high-resistivity second resin layer 728 b interposedtherebetween, on first lateral surface 12 c, second lateral surface 12d, and second end surface 12 f. Thus, first and second externalelectrodes 24 a, 24 b enable a reduced equivalent series resistance(ESR).

In order to form first and second resin layers 728 a, 728 b only on aportion of first and second main surfaces 12 a, 12 b and on a portion ofadjacent first and second end surfaces 12 e, 12 f, the following exampleof a method may be used. First, stacked bodies 12 are arranged on anarray plate, with their second main surface 12 b facing upward. Then,second main surface 12 b is masked, so that only a portion where a resinlayer is to be formed is exposed. Then, a resin-layer paste is appliedto second main surface 12 b by screen printing, for example. After that,the masking is removed. Similarly, a resin-layer paste is also appliedto first main surface 12 a and first and second end surfaces 12 e, 12 fby screen printing, for example.

As an alternative method to form first and second resin layers 728 a,728 b (only on a portion of first and second main surfaces 12 a, 12 band on a portion of adjacent first and second end surfaces 12 e, 12 f),the following example of a method may also be used. First, a resin-layerpaste is applied by, for example, dipping, not only to first and secondmain surfaces 12 a, 12 b and adjacent first and second end surfaces 12e, 12 f but also to other surfaces. Then, a superfluous resin-layerpaste on the surfaces other than first and second main surfaces 12 a, 12b and adjacent first and second end surfaces 12 e, 12 f is removed. Thisallows easy formation of first and second resin layers 728 a, 728 b.

9. Ninth Preferred Embodiment

FIG. 18 is an outside perspective view showing a multilayer ceramiccapacitor according to a ninth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

A multilayer ceramic capacitor 10I according to the ninth preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 828.Here, redundant description is omitted.

Resin layer 828 includes a first resin layer 828 a and a second resinlayer 828 b.

First resin layer 828 a covers first underlying electrode layer 26 alocated on second main surface 12 b and on first and second lateralsurfaces 12 c, 12 d adjacent to first end surface 12 e; and covers aportion of first underlying electrode layer 26 a located at the centralportion of first end surface 12 e.

Second resin layer 828 b covers second underlying electrode layer 26 blocated on second main surface 12 b and on first and second lateralsurfaces 12 c, 12 d adjacent to second end surface 12 f; and covers aportion of second underlying electrode layer 26 b located at the centralportion of second end surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10I is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 828 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10I.

Resin layer 828 also defines and functions as a protective layer toprevent water from entering internal electrode layers 16 throughunderlying electrode layer 26, thus improving the resistance tomoisture.

Further, all of second main surface 12 b and first and second lateralsurfaces 12 c, 12 d can define and function as a mounting surface, whicheliminates the need for distinction depending on the direction on anautomatic taping machine.

First plating layer 30 a covers first underlying electrode layer 26 alocated on first main surface 12 a and on first end surface 12 e, andcovers first resin layer 828 a located on second main surface 12 b, onfirst and second lateral surfaces 12 c, 12 d, and on first end surface12 e.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on first main surface 12 a and on second end surface 12 f, andcovers second resin layer 828 b located on second main surface 12 b, onfirst and second lateral surfaces 12 c, 12 d, and on second end surface12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 828 a interposed therebetween, onfirst main surface 12 a and first end surface 12 e. In second externalelectrode 24 b, second plating layer 30 b is directly in contact withsecond underlying electrode layer 26 b, with no high-resistivity secondresin layer 828 b interposed therebetween, on first main surface 12 aand second end surface 12 f. Thus, first and second external electrodes24 a, 24 b enable a reduced equivalent series resistance (ESR).

In order to form first and second resin layers 828 a, 828 b only on aportion of second main surface 12 b and on a portion of adjacent firstlateral surface 12 c, second lateral surface 12 d, first end surface 12e, and second end surface 12 f, the following example of a method may beused. First, stacked bodies 12 are arranged on an array plate, withtheir second main surface 12 b facing upward. Then, second main surface12 b is masked, so that only a portion where a resin layer is to beformed is exposed. Then, a resin-layer paste is applied to second mainsurface 12 b by screen printing, for example. After that, the masking isremoved. Similarly, a resin-layer paste is also applied to first andsecond lateral surfaces 12 c, 12 d and first and second end surfaces 12e, 12 f by screen printing, for example.

As an alternative method to form first and second resin layers 828 a,828 b (only on a portion of second main surface 12 b and on a portion ofadjacent first lateral surface 12 c, second lateral surface 12 d, firstend surface 12 e, and second end surface 12 f), the following example ofa method may also be used. First, a resin-layer paste is applied by, forexample, dipping, not only to second main surface 12 b and adjacentfirst and second lateral surfaces 12 c, 12 d and first and second endsurfaces 12 e, 12 f but also to other surfaces. Then, a superfluousresin-layer paste on the surfaces other than second main surface 12 band adjacent first and second lateral surfaces 12 c, 12 d and first andsecond end surfaces 12 e, 12 f is removed. This allows easy formation offirst and second resin layers 828 a, 828 b.

10. Tenth Preferred Embodiment

FIG. 19 is an outside perspective view showing a multilayer ceramiccapacitor according to a tenth preferred embodiment of the presentinvention in a state before the formation of a plating layer of externalelectrodes.

A multilayer ceramic capacitor 10J according to the tenth preferredembodiment is similar in configuration to multilayer ceramic capacitor10A according to the first preferred embodiment, except that resin layer28 in the first preferred embodiment is replaced by a resin layer 928.Here, redundant description is omitted.

Resin layer 928 includes a first resin layer 928 a and a second resinlayer 928 b.

First resin layer 928 a covers first underlying electrode layer 26 alocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to first end surface 12 e,and covers a portion of first underlying electrode layer 26 a located atthe central portion of first end surface 12 e.

Second resin layer 928 b covers second underlying electrode layer 26 blocated on first and second main surfaces 12 a, 12 b and on first andsecond lateral surfaces 12 c, 12 d adjacent to second end surface 12 f,and covers a portion of second underlying electrode layer 26 b locatedat the central portion of second end surface 12 f.

Accordingly, even if multilayer ceramic capacitor 10J is subjected tostresses due to the drop impact or bending stresses due to the thermalexpansion and contraction of a mounting board caused by thermal cycling,resin layer 928 can define and function as a buffer layer, thus reducingor preventing cracking of multilayer ceramic capacitor 10J.

Resin layer 928 also defines and functions as a protective layer toprevent water from entering internal electrode layers 16 throughunderlying electrode layer 26, thus improving the resistance tomoisture.

Further, all of first and second main surfaces 12 a, 12 b and first andsecond lateral surfaces 12 c, 12 d can define and function as a mountingsurface, which eliminates the need for distinction depending on thedirection on an automatic taping machine.

First plating layer 30 a covers first underlying electrode layer 26 alocated on first end surface 12 e, and covers first resin layer 928 alocated on first and second main surfaces 12 a, 12 b, on first andsecond lateral surfaces 12 c, 12 d, and on first end surface 12 e.

Second plating layer 30 b covers second underlying electrode layer 26 blocated on second end surface 12 f, and covers second resin layer 928 blocated on first and second main surfaces 12 a, 12 b, on first andsecond lateral surfaces 12 c, 12 d, and on second end surface 12 f.

Thus, in first external electrode 24 a, first plating layer 30 a isdirectly in contact with first underlying electrode layer 26 a, with nohigh-resistivity first resin layer 928 a interposed therebetween, onfirst end surface 12 e. In second external electrode 24 b, secondplating layer 30 b is directly in contact with second underlyingelectrode layer 26 b, with no high-resistivity second resin layer 928 binterposed therebetween, on second end surface 12 f. Thus, first andsecond external electrodes 24 a, 24 b enable a reduced equivalent seriesresistance (ESR).

In order to form first and second resin layers 928 a, 928 b only on aportion of first and second main surface, 12 a, 12 b and on a portion ofadjacent first lateral surface 12 c, second lateral surface 12 d, firstend surface 12 e, and second end surface 12 f, the following example ofa method may be used. First, stacked bodies 12 are arranged on an arrayplate, with their second main surface 12 b facing upward. Then, secondmain surface 12 b is masked, so that only a portion where a resin layeris to be formed is exposed. Then, a resin-layer paste is applied tosecond main surface 12 b by screen printing, for example. After that,the masking is removed. Similarly, a resin-layer paste is also appliedto first main surface 12 a, first and second lateral surfaces 12 c, 12d, and first and second end surfaces 12 e, 12 f by screen printing, forexample.

Alternatively, first and second resin layers 928 a, 928 b may be formedby applying a resin-layer paste by, for example, dipping, to all the sixfaces, and then removing a superfluous resin-layer paste.

Experimental Example 1. Multilayer Ceramic Capacitor in Working Example

As a working example, multilayer ceramic capacitors 10A according to thefirst preferred embodiment described above were produced according tothe above-described manufacturing method. The presence or absence ofcracking as a result of a substrate bending test and the ESR value wereexamined. The specifications of the capacitors in the working examplewere as follows.

-   -   Dimension L×W×T: about 3.2 mm×about 1.6 mm×about 1.6    -   Ceramic material: BaTiO₃    -   Capacitance: about 1 μF    -   Rated voltage: about 50 V    -   Internal electrodes: Ni    -   Structure of external electrodes    -   Underlying electrode layer    -   Material of underlying electrode layer: Electrode material        containing conductive metal (Cu) and glass component    -   Thickness of underlying electrode layer: About 80 μm (the        thickest portion at the center or approximate center of end        surfaces)    -   Resin layer    -   Thermosetting resin: Epoxy    -   Thickness of the thickest portion of first and second resin        layers at the center or approximate center in the length        direction of the first and second underlying electrode layers        located on the second main surface: about 30 μm    -   Plating layer    -   Double-layer structure composed of Ni and Sn plating layers    -   Thickness of Ni plating layer: about 3 μm    -   Thickness of Sn plating layer: about 4 μm

2. Multilayer Ceramic Capacitor in Comparative Example 1

As comparative example 1, multilayer ceramic capacitors with no resinlayer were produced. The presence or absence of cracking as a result ofa substrate bending test and the ESR value were examined. Thespecifications of the capacitors in comparative example 1 were asfollows.

-   -   Dimension L×W×T: about 3.2 mm×about 1.6 mm×about 1.6 mm    -   Ceramic material: BaTiO₃    -   Capacitance: about 1 μF    -   Rated voltage: about 50 V    -   Internal electrodes: Ni    -   Structure of external electrodes    -   Underlying electrode layer    -   Material of underlying electrode layer: Electrode material        containing conductive metal (Cu) and glass component    -   Thickness of underlying electrode layer: about 80 μm (the        thickest portion at the center or approximate center of end        surfaces)    -   Plating layer    -   Double-layer structure composed of Ni and Sn plating layers    -   Thickness of Ni plating layer: about 3 μm    -   Thickness of Sn plating layer: about 4 μm

3. Multilayer Ceramic Capacitor in Comparative Example 2

As comparative example 2, multilayer ceramic capacitors were producedhaving a thermosetting conductive resin layer between an underlyingelectrode layer and a plating layer. The presence or absence of crackingas a result of a substrate bending test and the ESR value were examined.The specifications of the capacitors in comparative example 2 were asfollows.

-   -   DimensionL×W×T: about 3.2 mm×about 1.6 mm×about 1.6 mm    -   Ceramic material: BaTiO₃    -   Capacitance: about 1 μF    -   Rated voltage: 50 V    -   Internal electrodes: Ni    -   Structure of external electrodes    -   Underlying electrode layer    -   Material of underlying electrode layer: Electrode material        containing conductive metal (Cu) and glass component    -   Thickness of underlying electrode layer: about 80 μm (the        thickest portion at the center or approximate center of end        surfaces)    -   Conductive resin layer    -   Metal filler of conductive resin layer: Ag-coated Cu    -   Resin of conductive resin layer: Epoxy (having a thermal curing        temperature of about 200° C.)    -   Thickness of the thickest portion of first and second conductive        resin layers at the center or approximate center in the height        direction of the first and second underlying electrode layers        located on the first and second end surfaces: about 80 μm    -   Thickness of the thickest portion of first and second conductive        resin layers at the center or approximate center in the length        direction of the first and second underlying electrode layers        located on the first and second main surfaces and on first and        second lateral surfaces: about 30 μm    -   The conductive resin layer was formed as follows: a conductive        resin paste containing a thermosetting resin and metal component        was applied to an underlying electrode layer; the conductive        resin paste was then heat-treated at a temperature of not less        than about 250° C. and not more than about 550° C. under a N₂        atmosphere; and then the resin was thermally cured.    -   Plating layer    -   Double-layer structure composed of Ni and Sn plating layers    -   Thickness of Ni plating layer: about 3 μm    -   Thickness of Sn plating layer: about 4 μm

4. Test Method

(1) Method of Bending Test

Multilayer ceramic capacitor samples were mounted on a JEITA standardsubstrate with lands using LF solder by reflowing under a peaktemperature of about 250° C. From the side opposite to thecapacitor-mounted face of the substrate, a mechanical stress was appliedto the substrate to cause a certain amount of deflection (about 5 mm),using a pushing tool having a curvature radius R of about 230 mm. Afterthat, the capacitor samples were removed from the substrate, and crosssection polishing was performed on a lateral surface of each sample inthe direction of a line connecting the two lateral surfaces. Using amicroscope, cracking was examined in cross sections at three locations:at the location where the internal electrodes started to appear, at thecenter in the W dimension, and at the location where the internalelectrodes disappeared. The number of samples was ten, each with threelocations.

(2) Method of Measuring Equivalent Series Resistance (ESR)

The equivalent series resistance (ESR) was measured using a precisionLCR meter (E4980A, manufactured by Agilent Technologies, Inc.) at ameasurement frequency of about 1 MHz and with a measurement voltage ofabout 500 mV. The number of samples was ten.

The measurement results of ESR are shown in table 1, and the results ofbending test are shown in table 2.

TABLE 1 ESR(mΩ) Sample Working Comparison Comparison No. example example1 example 2 1 8.57 7.43 20.05 2 7.68 7.56 20.40 3 7.92 7.52 17.66 4 7.787.51 18.12 5 8.21 7.72 18.81 6 8.11 7.57 18.94 7 7.92 7.57 20.20 8 7.758.31 19.67 9 8.60 7.38 19.23 10 8.01 7.91 19.10 Average 8.06 7.65 19.22Maximum 8.60 8.31 20.40 Minimum 7.68 7.38 17.66 Standard 0.32 0.28 0.86deviation

TABLE 2 Number of cracked samples Working Comparison Comparison exampleexample 1 example 2 Location where 0/30 18/30 0/30 internal electrodesstart to appear Center in 0/30 16/30 0/30 W dimension Location where0/30 16/30 0/30 internal electrodes disappear

Table 1 shows that the capacitors in the working example have a lowerESR. Each of these capacitors includes external electrodes including anunderlying electrode layer, a resin layer, and a plating layer, wherethe underlying electrode layer is exposed through the resin layer anddirectly in contact with the plating layer, and where the resin layercontains a thermosetting resin and no metal component. On the otherhand, the capacitors in comparative example 2 include externalelectrodes including an epoxy thermosetting conductive resin layercontaining metallic powder. The contact of the metallic powder providesa current-carrying path, thus increasing the resistance value and thusincreasing the ESR.

Further, Table 2 shows that the capacitors in the working example can beprevented from cracking. Each of these capacitors includes externalelectrodes including an underlying electrode layer and a plating layer,with a resin layer interposed therebetween, where the resin layercontains a thermosetting resin and no metal component. Accordingly, evenif the capacitor is subjected to bending stresses, the resin layer candefine and function as a buffer layer, thus preventing cracking of thecapacitor. On the other hand, the capacitors in comparative example 1include no resin layer. Therefore, when bending stresses occur, theexternal electrodes cannot release the stresses applied to the mountingboard (the deformation of the mounting board) and thus cannot preventcracking.

While preferred embodiments of the present invention have been describedabove, it is to be understood that variations and modifications will beapparent to those skilled in the art without departing from the scopeand spirit of the present invention. The scope of the present invention,therefore, is to be determined solely by the following claims.

What is claimed is:
 1. A multilayer ceramic electronic componentcomprising: a stacked body including a plurality of ceramic layers and aplurality of internal electrode layers which are stacked, the stackedbody including a first main surface and a second main surface oppositeto each other in a stacking direction, a first end surface and a secondend surface opposite to each other in a length direction orthogonal toor substantially orthogonal to the stacking direction, and a firstlateral surface and a second lateral surface opposite to each other in awidth direction orthogonal to or substantially orthogonal to thestacking direction and the length direction; a first external electrodedisposed on the first end surface; and a second external electrodedisposed on the second end surface; wherein the second main surface ofthe stacked body defines and functions as a mounting surface; the firstexternal electrode includes: a first underlying electrode layerincluding a conductive metal; a first resin layer including a resin andno metal component; and a first plating layer; the second externalelectrode includes: a second underlying electrode layer including aconductive metal; a second resin layer including a resin and no metalcomponent; and a second plating layer; the first underlying electrodelayer covers the first end surface, extends from the first end surface,and covers a portion of each of the first main surface, the second mainsurface, the first lateral surface, and the second lateral surface; thesecond underlying electrode layer covers the second end surface, extendsfrom the second end surface, and covers a portion of each of the firstmain surface, the second main surface, the first lateral surface, andthe second lateral surface; the first resin layer covers the firstunderlying electrode layer at least on the second main surface adjacentto the first end surface; the second resin layer covers the secondunderlying electrode layer at least on the second main surface adjacentto the second end surface; the first plating layer covers a portion of asurface of the first underlying electrode layer that is not covered withthe first resin layer, and completely covers the first resin layer; andthe second plating layer covers a portion of a surface of the secondunderlying electrode layer that is not covered with the second resinlayer, and completely covers the second resin layer.
 2. The multilayerceramic electronic component according to claim 1, wherein the firstresin layer located on the second main surface extends to a portion ofthe first end surface; and the second resin layer located on the secondmain surface extends to a portion of the second end surface.
 3. Themultilayer ceramic electronic component according to claim 1, whereinthe first resin layer covers the first underlying electrode layer on thefirst main surface adjacent to the first end surface; and the secondresin layer covers the second underlying electrode layer on the firstmain surface adjacent to the second end surface.
 4. The multilayerceramic electronic component according to claim 3, wherein the firstresin layer located on the first main surface extends to a portion ofthe first end surface, and the second resin layer located on the firstmain surface extends to a portion of the second end surface.
 5. Themultilayer ceramic electronic component according to claim 1, whereinthe first resin layer covers the first underlying electrode layer on thefirst lateral surface and on the second lateral surface adjacent to thefirst end surface; and the second resin layer covers the secondunderlying electrode layer on the first lateral surface and on thesecond lateral surface adjacent to the second end surface.
 6. Themultilayer ceramic electronic component according to claim 5, whereinthe first resin layer located on the first lateral surface and on thesecond lateral surface adjacent to the first end surface extends to aportion of the first end surface; and the second resin layer located onthe first lateral surface and on the second lateral surface adjacent tothe second end surface extends to a portion of the second end surface.7. The multilayer ceramic electronic component according to claim 1,wherein the first resin layer covers the first underlying electrodelayer on the first end surface, the first resin layer located on thefirst end surface being separate from the first resin layer located onthe second main surface adjacent to the first end surface; and thesecond resin layer covers the second underlying electrode layer on thesecond end surface, the second resin layer located on the second endsurface being separate from the second resin layer located on the secondmain surface adjacent to the second end surface.
 8. The multilayerceramic electronic component according to claim 7, wherein the firstresin layer covers the first underlying electrode layer on the firstmain surface adjacent to the first end surface; and the second resinlayer covers the second underlying electrode layer on the first mainsurface adjacent to the second end surface.
 9. The multilayer ceramicelectronic component according to claim 7, wherein the first resin layercovers the first underlying electrode layer on the first lateral surfaceand on the second lateral surface adjacent to the first end surface; andthe second resin layer covers the second underlying electrode layer onthe first lateral surface and on the second lateral surface adjacent tothe second end surface.
 10. The multilayer ceramic electronic componentaccording to claim 1, wherein the stacked body includes rounded cornersand rounded ridge lines.
 11. The multilayer ceramic electronic componentaccording to claim 1, wherein the stacked body includes an effectivelayer portion, a first outer layer portion, and a second outer layerportion; the effective layer portion includes the plurality of internalelectrode layers and ceramic layers of the plurality of ceramic layersdisposed therebetween; and the effective layer portion is between thefirst and second outer layer portions.
 12. The multilayer ceramicelectronic component according to claim 1, wherein dimensions of thestacked body are not less than about 0.2 mm and not more than about 10.0mm in the length direction, not less than about 0.1 mm and not more thanabout 10.0 mm in the width direction, and not less than about 0.1 mm andnot more than about 5.0 mm in the stacking direction.
 13. The multilayerceramic electronic component according to claim 1, wherein the pluralityof ceramic layers are made of a dielectric ceramic including at leastone of BaTiO₃, CaTiO₃, SrTiO₃, or CaZrO₃ as a primary component.
 14. Themultilayer ceramic electronic component according to claim 13, whereinthe plurality of ceramic layers include at least one of Mn compounds, Fecompounds, Cr compounds, Co compounds, and Ni compounds as a secondarycomponent.
 15. The multilayer ceramic electronic component according toclaim 1, wherein the plurality of internal electrode layers include aplurality of first internal electrode layers and a plurality of secondinternal electrode layers that are alternately disposed in the stackingdirection; the plurality of first internal electrode layers areelectrically connected to the first external electrode; and theplurality of second internal electrode layers are electrically connectedto the second external electrode.
 16. The multilayer ceramic electroniccomponent according to claim 1, wherein the conductive metal of each ofthe first and second underlying electrode layers includes at least oneof Cu, Ni, Ag, Pb, Pd, Ag—Pb alloy, Ag—Pd alloy, and Au.
 17. Themultilayer ceramic electronic component according to claim 1, whereineach of the first and second underlying electrode layers includes aglass component in addition to the conductive metal.
 18. The multilayerceramic electronic component according to claim 17, wherein the glasscomponent includes at least one of B, Si, Ba, Mg, Al, and Li.
 19. Themultilayer ceramic electronic component according to claim 1, whereineach of the first and second underlying electrode layers has a thicknessof not less than about 10 μm and not more than about 150 μm on therespective first and second end surfaces.
 20. The multilayer ceramicelectronic component according to claim 1, wherein each of the first andsecond plating layers includes a lower plating layer provided on thestacked body and an upper plating layer provided on the lower platinglayer.